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组合逻辑电路中软错误率的频域分析方法
  • 摘要

    基于频域的软错误率分析方法可实现快速而精确地分析组合逻辑中软错误的电气屏蔽特性和窗闩屏蔽特性.该方法利用信号和逻辑门的频域特性,计算瞬时错误信号在组合逻辑电路中传播过程.基于频域的分析方法主要分为2个处理步骤:线性系统处理和非线性系统处理.线性系统处理通过电路系统的频率响应来计算输出信号.非线性系统处理瞬时信号的幅度过高而导致晶体管工作在不同的线性系统的情况.基于频域的分析方法采用电路系统的输入输出特性来计算非线性系统的输出信号.数据拟合的方法可以求解粒子击中而导致的瞬时错误信号的信号宽度和通路输出信号的信号宽度之间的函数关系.二者结合可计算由粒子撞击而导致错误信号的概率.使用反相器链的实验结果表明,相对于HSPICE仿真,基于频域的软错误率分析方法是高效的,且可以取得平均96.96%的精确度.使用IsCAS'85基准电路和乘法器阵列的实验结果表明,基于频域的软错误率分析方法取得95.82%的精确度.

  • 作者

    雷韶华  韩银和  李晓维  Lei Shaohua  Han Yinhe  Li Xiaowei 

  • 作者单位

    中国科学院计算技术研究所计算机系统结构重点实验室,北京,100190/中国科学院研究生院,北京,100190

  • 刊期

    2011年3期 ISTIC EI PKU

  • 关键词

    软错误率  电气屏蔽特性  窗闩屏蔽特性  逻辑屏蔽特性  重汇聚 

参考文献
  • [1] 王京,杨波. 低轨卫星微电子器件SER仿真分析. 电子质量, 2005,7
  • [2] Ziegler JF.. TERRESTRIAL COSMIC RAYS. IBM journal of research and development, 1996,1
  • [3] Hazucha P.;Svensson C.. Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Transactions on Nuclear Science, 2000,6
  • [4] Rajeev R. Rao;Kaviraj Chopra;David T. Blaauw;Dennis M. Sylvester. Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: A publication of the IEEE Circuits and Systems Society, 2007,3
  • [5] Kaul N.;Bhuva B.L.. Simulation of SEU transients in CMOS ICs. IEEE Transactions on Nuclear Science, 1991,6
  • [6] Zhang M;Shanbhag N. A soft error rate analysis methodology. Washington,DC:IEEE Computer Society, 2004
  • [7] Dahlgren P;Liden P. A switch-level algorithm for simulation of transient in combinational logic. Piscataway,NJ:IEEE, 1995
  • [8] Cha H;Rudnick E M;Patel J H. A gatelevel simulation environment for alpha-particle-induced transient faults. IEEE Transactions on Computer, 1996,11
  • [9] Mohanram K. Simulation of transients caused by single-event upsets in combinational logic. Piscataway,NJ:IEEE, 2005
  • [10] Horowitz M A. Timing models for MOS circuits. Standford,California:Stanford University, 1984
  • [11] Dhillon Y S;Diril A U;Chatterjee A. Soft-error tolerance analysis and optimization of nanometer circuits. Washington,DC:IEEE Computer Society, 2005
  • [12] Zhao C;Bai X L;Dey S. A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. New York:ACM, 2004
  • [13] Garg R;Nagpal C;Khatri S P. A fast,analytical estimator for the SEU-indueed pulse width in combinational designs. New York:ACM, 2008
  • [14] Lei S H;Han Y H;Li X W. Frequency analysis method for propagation of transient errors in combinational logic. Piseataway,NJ:IEEE, 2007
  • [15] Ramanarayanan R;Degalahal V;Vijaykrishnan N. Analysis of soft error rate in flip-flop and scannable latches. Piscataway,NJ:IEEE, 2003
  • [16] Shivakumar P;Kistler M;Keckler S W. Modeling the effect of technology trends on the soft error rate of combinatorial logic. Washington,DC:1EEE Computer Society, 2002
  • [17] Simon H;aykin Barry Van Veen. 信号与系统. 北京:电子工业出版社, 2004
  • [18] 朱绍箕. 非线性系统的近似分析方法. 北京:国防工业出版社, 1980
  • [19] Ercolani S;Favalli M;Damiani M. Estimation of signal probability in combinational logic networks. Washington,DC:IEEE Computer Society, 1989
  • [20] Arizona State University. Predictive technology model. http://www.eas.asu.edu/~ptm, 2007-03-01
  • [21] Feng W;Yuan X;Rajaraman R. Soft error rate analysis for combinational logic using an accurate electrical masking model. Piscataway,NJ:IEEE, 2007
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