登录 | 注册 | 退出 | 公司首页 | 繁体中文 | 满意度调查
综合馆
基于类型预测的甚块预测器
  • 摘要

    高性能的甚块预测器是保证EDGE体系结构性能的关键手段.为研究性能更好的甚块预测器,文中通过仿真实验发现甚块的出口类型独立于甚块的出口个数和甚块的动态执行结果而存在.以此为据,提出了基于类型预测的甚块预测器.该预测器摈弃了甚块出口号,直接对甚块出口类型进行预测.随后,根据对甚块出口类型可预测性的分析,通过实验证明甚块出口类型与历史和路径信息相关.仿真结果显示,与经典的基于出口预测的甚块预测器相比,文中提出的基于类型预测的甚块预测器能够将每千条指令误预测次数平均降低约10%.

  • 作者

    苟鹏飞  喻明艳  杨兵  李清波  王诗博  GOU Peng-Fei  YU Ming-Yan  YANG Bing  LI Qing-Bo  WANG Shi-Bo 

  • 作者单位

    哈尔滨工业大学微电子中心 哈尔滨150001

  • 刊期

    2012年7期 ISTIC EI PKU

  • 关键词

    甚块预测器  分支预测器  EDGE体系结构  出口类型预测  可预测性 

参考文献
  • [1] Nathan L. Binkert;Ronald G. Dreslinski;Lisa R. Hsu;Kevin T. Lim;Ali G. Saidi;Steven K. Reinhardt. THE M5 SIMULATOR: MODELING NETWORKED SYSTEMS. IEEE Micro, 2006,4
  • [2] Michael Van Biesbrouck Brad Calder;Lieven Eeckhout. EFFICIENT SAMPLING STARTUP FOR SIMPOINT. IEEE Micro, 2006,4
  • [3] Shalf J;Asanovic K;Patterson D. The manycore revolution:Will HPC community lead or folow. SciDAC Review, 2009,14
  • [4] McDonald R;Burger D;Keckler S W. TRIPS processor reference manual.[Technical Report TR-05-19]. Department of Computer Science,University of Texas at Austin, 2005
  • [5] Gebhart M;Maher B A;Coons K E. An evaluation of the trips computer system. Washington,DC:USA, 2009
  • [6] Ranganathan N;Nagarajan R;Jiménez D. Combining hyperblocks and exit prediction to increase front-end bandwidth and performance.[Technical Report TR-02-41]. Department of Computer Science,University of Texas at Austin, 2002
  • [7] Ranganathan N. Control flow speculation for distributed architectures. The University of Texas at Austin,United States,Texas, 2009
  • [8] Hao E;Chang P Y;Evers M. Increasing the instruction fetch rate via block-structured instruction set architectures. France:Paris, 1996
  • [9] Jacobson Q;Rotenberg E;Smith J. Path-based next trace prediction. Research Triangle Park,North Carolina,USA, 1997
  • [10] Patel S;Lumetta S. Replay:A hardware framework for dynamic optimization. IEEE Transaction on Computer, 2001,06
  • [11] Asanovic K;Bodik R;Demmel J. A view of the parallel computing landscape. Communications of the ACM, 2009,10
  • [12] Zmily A;Kozyrakis C. Block-aware instruction set architecture. ACM Transactions on Architecture and (Code Optimization, 2006,03
  • [13] Sohi G;Breach S;Vijaykumar T. Multiscalar processors. Santa Margherita Ligure,Italy, 1995
  • [14] Esmaeilzadeh H;Burger D. Hierarchical control prediction:Support for aggressive predication. Austin,Texas,USA, 2009
  • [15] Seznec A;Michaud P. A case for (partially)-tagged geometric history length predictors. Journal of Instruction Level Parallelism, 2006,01
  • [16] Chang P Y;Hao E;Patt Y. Target prediction for indirect jumps. Denver,Colorado,USA, 1997
  • [17] Driesen K;Holzle U. The cascaded predictor:Economical and adaptive branch target prediction. Dallas,TX,USA, 1998
  • [18] McFarling S. Combining branch predictors.[Technical Report TN-36]. Digital Western Research Laboratory,Palo Alto,CA,USA, 1993
  • [19] Guo Pengfei;Li Qingbo;Jin Yinghan. M5 based edge architecture modeling. Amsterdam:Netherlands, 2010
  • [20] Mahlke S;Lin D;Chen W. Effective compiler support for predicated execution using the hyperblock. Portland:Oregon, 1992
  • [21] Ranganathan N;Burger D;Keckler S. Analysis of the trips prototype block predictor. Boston,MA,USA, 2009
  • [22] Jacobson Q;Bennett S;Sharma N. Control flow speculation in multiscalar processors. San Antonio,Texas,USA, 1997
  • [23] Yoder B;Burrill J;Mcdonald R. Software infrastructure and tools for the trips prototype. San Diego,California,USA, 2007
  • [24] Eyerman S;Eeckhout L. Modeling critical sections in Amdahl's law and its implications for multicore design. Saint-Malo,France, 2010
  • [25] Esmaeilzadeh H;Blem E;Amant R St. Dark silicon and the end of multicore scaling. San Jose,California,U.S.A, 2011
  • [26] Burger D;Keckler S W;McKinley K S. Scaling to the end of silicon with edge architectures. IEEE Transaction on Computer, 2004,07
  • [27] Nagarajan R;Kushwaha S K;Burger D. Static placement,dynamic issue (SPDI) scheduling for edge architectures. Antibes Juan-les-Pins,France, 2004
  • [28] Sankaralingam K;Nagarajan R;Liu H. Exploiting ILP,TLP,and DLP with the polymorphous trips architecture. San Diego,California,USA, 2003
  • [29] Sankaralingam K;Nagarajan R;McDonald R G. Distributed microarchitectural protocols in the trips prototype processor. Orlando,Florida,USA, 2006
  • [30] Hill M D;Marty M R. Amdahl's law in the multicore era. IEEE Transaction on Computer, 2008,07
  • [31] Evers M;Patel S;Patt Y. An analysis of correlation and predictability:What makes two level branch predictors work. Spain:Barcelona, 1998
  • [32] Loh G. A simple divide-and-conquer approach for neuralclass branch prediction. Saint Louis,MO,USA, 2005
查看更多︾
相似文献 查看更多>>
3.233.221.149